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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 1. |  MC74HC112A | Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | ON Semiconductor | ONSEMI | - | - | - | 173 Kb |
| 2. | IN74HC112A | Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS | IK Semicon Co., Ltd | IKSEMICON | - | - | - | 159 Kb |
| 3. | KK74HC112A | Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS | KODENSHI KOREA CORP. | KODENSHI | - | - | - | 168 Kb |
| 4. | SN74LVC112A | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 5. | LC503UHR1-30P-A-C112A | 5-mm Round LED | Cree, Inc | CREE | - | - | - | 303 Kb |
| 6. | 20020110-C112A01LF | TERMINAL BLOCK PLUGGABLESOCKET RIGHT ANGLE | FCI connector | FCICONNECTOR | - | - | - | 366 Kb |
| 7. | IN74HC112AD | Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS | IK Semicon Co., Ltd | IKSEMICON | - | - | - | 159 Kb |
| 8. | KK74HC112AD | Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS | KODENSHI KOREA CORP. | KODENSHI | - | - | - | 168 Kb |
| 9. | SN74LVC112AD | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 10. | SN74LVC112ADB | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 11. | SN74LVC112ADBLE | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 12. | SN74LVC112ADBR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 13. | SN74LVC112ADBRE4 | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 14. | SN74LVC112ADE4 | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 15. | MC74HC112ADG | Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | ON Semiconductor | ONSEMI | - | - | - | 173 Kb |
| 16. | SN74LVC112ADGV | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 17. | SN74LVC112ADGVR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 18. | SN74LVC112ADGVRE4 | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 19. | SN74LVC112ADR | DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | Texas Instruments | TI | - | - | - | 291 Kb |
| 20. | MC74HC112ADR2G | Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | ON Semiconductor | ONSEMI | - | - | - | 173 Kb |
