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| # | Part: | Description: | Manuf. | Package | Pins | T°min | T°max | PDF size |
| 1. |  74LS11 | TRIPLE 3-INPUT AND GATE | List of Unclassifed Manufacturers | ETC | - | - | - | 59 Kb |
| 2. | 74LS11 | TRIPLE 3-INPUT AND GATE | List of Unclassifed Manufacturers | ETC | - | - | - | 59 Kb |
| 3. | 74LS11 | Triple 3-Input AND Gate | Fairchild Semiconductor | FAIRCHILD | - | - | - | 50 Kb |
| 4. | DM74LS11 | Triple 3-Input AND Gates | National Semiconductor | NSC | - | - | - | 127 Kb |
| 5. | DM74LS11 | Triple 3-Input AND Gate | Fairchild Semiconductor | FAIRCHILD | - | - | - | 50 Kb |
| 6. | HD74LS11 | Triple 3-input Positive AND Gates (with Open Collector Outputs) | Renesas Technology Corp | RENESAS | - | - | - | 93 Kb |
| 7. | HD74LS11 | Triple 3-input Positive AND Gates(with Open Collector Outputs) | Hitachi Semiconductor | HITACHI | - | - | - | 53 Kb |
| 8. | SN74LS11 | TRIPLE 3-INPUT POSITIVE-AND GATES | Texas Instruments | TI | - | - | - | 179 Kb |
| 9. | SN74LS11 | TRIPLE 3-INPUT POSITIVE-AND GATES | Texas Instruments | TI | - | - | - | 159 Kb |
| 10. | HD74LS11 | Ouadruple 2-input Positive NAND Gates | Hitachi Semiconductor | HITACHI | - | - | - | 5.74 Mb |
| 11. | 74LS112 | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | Texas Instruments | TI | - | - | - | 291 Kb |
| 12. | 74LS112 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | Fairchild Semiconductor | FAIRCHILD | - | - | - | 57 Kb |
| 13. | 74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | Hitachi Semiconductor | HITACHI | - | - | - | 81 Kb |
| 14. | 74LS112 | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola, Inc | MOTOROLA | - | - | - | 152 Kb |
| 15. | HD74LS112 | Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) | Hitachi Semiconductor | HITACHI | - | - | - | 81 Kb |
| 16. | HD74LS112 | Ouadruple 2-input Positive NAND Gates | Hitachi Semiconductor | HITACHI | - | - | - | 5.74 Mb |
| 17. | SN74LS112 | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | Texas Instruments | TI | - | - | - | 291 Kb |
| 18. | DM74LS112A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs | Fairchild Semiconductor | FAIRCHILD | - | - | - | 57 Kb |
| 19. | DM74LS112A | DUAL NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS WITH PRESET, CLEAR, AND COMPLEMENTARY OUTPUTS | National Semiconductor | NSC | - | - | - | 107 Kb |
| 20. | SN74LS112A | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR | Texas Instruments | TI | - | - | - | 291 Kb |
| 21. | SN74LS112A | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WIITH PRESET AND CLEAR | Texas Instruments | TI | - | - | - | 678 Kb |
